This invention relates to a data output device included in a double data rate (DDR) SDRAM; and more particularly, to a data output device included in a DDR SDRAM wherein data are outputted in synchronization with a rising edge and a falling edge of a clock signal
Generally, a conventional single data rate (SDR) synchronous memory device outputs data in synchronization with a rising edge of a clock signal. On the other hand, a double data rate (DDR) synchronous memory device outputs data in synchronization with the rising edge and a falling edge of the clock signal.
FIG. 1 is a block circuit diagram illustrating a synchronous memory device including a conventional data output device.
The synchronous memory device outputs data at a high speed, which a wave pipeline technique is applied to. In the wave pipeline technique, a plurality of registers are used. The wave pipeline technique is also applied to the DDR synchronous memory device wherein bandwidth can be significantly increased.
Referring to FIG. 1, a command decoder 120 receives command signal inputted to the memory device. The command decoder 120 generates corresponding signals by decoding the received command signal.
For example, when the command decoder 120 receives a read command signal 101 including a chip select signal (/CS), a row address strobe signal (/RAS), a column address strobe signal (/CAS) and a write enable signal (/WE), the command decoder 120 generates a read signal 122 and a bst_end signal 124. The read signal 122 contains information of xe2x80x9cbegin a read operationxe2x80x9d and the bst_end signal 124 contains information of burst length.
The read signal 122 and the bst_end signal 124, together with a cas latency signal 132 from a mode register 130 and an internal clock (iclk) signal 112 from a clock buffer 110, are inputted to data output controlling unit 170, and in response, the data output control unit 170 generates one or more pipe input (pin) signals 180 and one or more pipe out (pout) signals 182. Here, the cas latency signal 132 is programmed in the mode register 130 and the iclk signal 112 is generated in the clock buffer 110. Each pin signal 180-0xcx9c180-n controls data to be inputted to each of a plurality of registers 190-0xcx9c190-n and each pout signal 192-0xcx9c182-n controls data signals to be outputted from each register.
(n+1) column address signals are inputted to (n+1) column address buffers 140 and then, internal column address signal (ca less than 0:n greater than ) 142 is generated and outputted from the column address buffer 140. Upon a burst read operation, the ca less than 0:n greater than  142 is inputted to a burst column address counter 150, used as a start address signal.
The burst column address counter 150 transmits a column address to a column address decoder 160 in synchronization with the iclk signal 112 and the column address decoder 160 generates and outputs a signal (Yi) 165.
A bit line sense amplifier 210 is selected, based on the signal Yi 165. As a word line 211 is selected by a bank active command signal (not shown), data stored in a cell capacitor 214 are loaded on a bit line 212 and then sensed and amplified by the bit line sense amplifier 210.
The data amplified by the bit line sense amplifier 210, are loaded on a local input output line (local IO) and then sensed and amplified by input output (IO) sense amplifier 220. The data amplified by the IO sense amplifier 220 are loaded on a global input output line (global IO) 230.
Each of pipe input signals (pin less than 0:n greater than ) 180-0xcx9c180-n outputted from the data output control unit 170 controls corresponding input switches 184-0xcx9c184-n that are coupled to each of registers 190-0xcx9c190-n in order to store the data loaded on the global IO 230 in each register sequently. Thus, if there are n registers, also there are needed n pipe input signals.
Each of pipe output signals (pout less than 0:n greater than ) 182-0xcx9c182-n outputted from the data output control unit 170 controls corresponding output switches 186-0xcx9c186-n that are coupled to each of registers 190-0xcx9c190-n and an output driver 200. According to the output switch control, the data stored in each register are transmitted to the output driver 200 sequentially to thereby generate output data (DQ) 210. Thus, if there are n registers, also there are needed n pipe output signals.
FIG. 2 is a timing chart illustrating data output in a synchronous memory device shown in FIG. 1 wherein cas latency (CL)=3 and burst length=4.
The memory device receives an external clock (CLK) signal and then generates an internal clock (iclk) signal. A first pipe output signal (pout) is enabled, (CL-1) clock periods after the read command signal is inputted. Next pipe out signals are enabled sequently as long as the burst length.
Data are outputted under control of each pipe output signal, after a clock access time (tAC) from the (CL-1) clock periods after the read command signal is inputted. The outputted data are held during a output hold time (tOH).
As described above, data can be outputted at a high speed by applying the wave pipeline technique also to the DDR SDRAM. However, because the data can be outputted in synchronization with the rising edge and the falling edge of the clock signal in the DDR SDRAM wherein 2-bit prefetch mode is applied to, there is needed a newly-designed data output device in the DDR SDRAM in order to apply the 2-bit prefetch mode and the wave pipeline technique to the DDR SDRAM to thereby output the data at a higher speed.
It is an object of the present invention to provide an apparatus for outputting data included in a synchronous memory device to thereby operate the synchronous memory with stability at frequency higher than 200 MHz.
In accordance with an aspect of the present invention, there is provided an apparatus for outputting data included in a synchronous memory device, the apparatus including: first storage means for storing in sequence even data provided by a first sense amplifier coupled to a selected even bank; second storage means for storing odd data in sequence provided by a second sense amplifier coupled to a selected odd bank; selection means coupled to the first storage means and the second storage means, for receiving at the same time both the even data and the odd data; third storage means for storing and providing one of both the even data and the odd data in synchronization with a rising edge of a clock signal; fourth storage means for storing and providing one of both the even data and the odd data in synchronization with a falling edge of a clock signal; data output means for driving data from third storage means and data from the fourth storage means.